Naslov (srp)

Poboljšanje performansi asimetričnih višejezgarnih procesora kroz migraciju transakcija i prilagođenje podsistema keš memorija : doktorska disertacija

Autor

Šuštran, Živojin, 1987-

Doprinosi

Cvetanović, Miloš, 1978-
Radivojević, Zaharije, 1978-
Kovačević, Miloš, 1968-
Tomašević, Milo, 1957-
Protić, Jelica, 1962-

Opis (eng)

Existing trends in computer design aim to raise the performance of computer systems tothe highest possible level in order to meet the needs for processing large amounts of data. Attentionis focused on the design of a processor as the main actor in the data processing process. Improvementtrends in processor performance predicted by Moore’s Law has been slowing down recently due tophysical limitations of semiconductor technology and increasing performance is getting harder andharder. This problem is attempted to be compensated by various techniques aimed at improvingperformance without increasing transistor and power consumption.In this thesis, asymmetric multicore processors with support for transactional memory are considered.Two new techniques have been proposed to increase the performance of such processors. Onetechnique aims to reduce transaction congestion due to high parallelism by migrating transactions toa faster core. The transactions that contribute the most to an occurrence of congestion are selected formigration. Executing them on a faster core reduces their chances of conflict with other transactionsand thus increases the chance of avoiding congestion. Another technique adjusts the cache subsystemto reduce caches’ access latency and to reduce the chances of false conflicts while reducing the numberof transistors required to implement the cache. This can be achieved by using small and simplecaches.Detailed implementation proposals are given for both techniques. Prototypes of these techniqueswere made in the Gem5 simulator, which models processor’s system in detail. Using prototypes, theproposed techniques were evaluated by simulating a large number of applications from a standardbenchmark set for transactional memory. The analysis of the simulation results gave suggestions onhow and when the proposed techniques should be used.

Opis (srp)

Postojeći pravci razvoja računarstva imaju za cilj da se performanse računarskih sistemapodignu na što viši nivo, da bi se zadovoljile potrebe za obradom velike količine podataka...

Opis (srp)

Elektrotehnika i računarstvo - Računarska tehnika i informatika / Electrical Engineering and Computing - Computer Engineering and Informatics Datum odbrane: 25.11.2021.

Jezik

srpski

Datum

2021

Licenca

Ovo delo je licencirano pod uslovima licence
Creative Commons CC BY-NC-ND 3.0 AT - Creative Commons Autorstvo - Nekomercijalno - Bez prerada 3.0 Austria License.

http://creativecommons.org/licenses/by-nc-nd/3.0/at/legalcode

Predmet

OSNO - Opšta sistematizacija naučnih oblasti, Primenjena kibernetika

OSNO - Opšta sistematizacija naučnih oblasti, Softversko inženjerstvo

asymmetric multiprocessors, homogeneous instruction set, transactional memory, cache subsystem, Gem5

OSNO - Opšta sistematizacija naučnih oblasti, Primenjena kibernetika

OSNO - Opšta sistematizacija naučnih oblasti, Softversko inženjerstvo

asimetrični višejezgarni procesori, homogeni instrukcijski set, transakciona memorija, podsistem keš memorija, Gem5